Certain memory cells, e.g., flash memory cells, include at least one floating gate programmed and erased through one or more program/erase gates, word lines, or other conductive element(s). Some memory cells use a common program/erase gate extending over a floating gate to both program and erase the cell. In some implementations, the floating gate is formed by a Poly1 layer, while the program/erase gate is formed by a Poly2 layer that partially overlaps the underlying Poly1 floating gate in the lateral direction. For some memory cells, the manufacturing process includes a floating gate thermal oxidation process that forms a football-shaped oxide over the Poly 1 floating gate, as discussed below.
FIG. 1 illustrates a partial cross-sectional view of an example memory cell 10A, e.g., a flash memory cell, including a Poly1 floating gate 14 and an overlying football-shaped oxide region (“football oxide”) 16 formed over a substrate 12, and a Poly2 gate 18 (e.g., a word line, erase gate, or common program/erase gate) extending partially over the floating gate 14. The football oxide 16 is formed over the floating gate 14 by a thermal oxidation process on floating gate 14, which defines upwardly-pointing tips 15 at the edges of floating gate 14. These FG tips 15 may define a conductive coupling to adjacent program/erase gates, e.g., the Poly2 gate 18 shown in FIG. 1.
After forming the floating gate 14 and football oxide 16, a source dopant implant may be performed, which is self-aligned by the lateral edge of the floating gate 14, followed by an anneal process that diffuses the source dopant outwardly such that the resulting source region extends partially under the floating gate 14, as shown in FIG. 1. However, during the source dopant implant, a portion of the dopant may penetrate through the football oxide 16 and into the underlying floating gate 14, which may result in a dulling or blunting of one or more floating gate tips 15, e.g., after subsequent oxidation steps (wherein the dopant absorbed in the floating gate 14 promotes oxidation of the floating gate tips 15). This dulling or blunting of the floating gate tip(s) 15 may decrease the efficiency of erase and/or program operations of the memory cell 10A.
FIGS. 2A and 2B illustrate example cross-sections taken at selected times during a conventional manufacturing process for the conventional memory cell 10A shown in FIG. 2, e.g., a flash memory cell including multiple floating gates. As shown in FIG. 2A, a Poly1 layer 30 may be deposited over a silicon substrate. A nitride layer may then be deposited and patterned using known techniques to form a hard mask 32. As shown in FIG. 2B, a floating gate oxidation process may then be performed, which forms a football oxide 16 over areas of the Poly1 layer 30 exposed through the nitride mask 32 (which subsequently defines the floating gates 14). The nitride mask 32 may subsequently be removed, followed by a plasma etch to remove portions of the Poly1 layer 30 uncovered by each football oxide 16, which defines the lateral extent of each floating gate 14. This may be followed by a source implant and/or formation of a Poly2 layer (e.g., to form a word line, erase gate, coupling gate, etc.), depending on the particular implementation.
FIG. 3 illustrates another example mirrored memory cell 10B (e.g., a SuperFlash cell) including two spaced-apart floating gates 14, a word line 20 formed over each floating gate 14, and a common erase gate or “coupling gate” 22 formed between and extending over both floating gates 14 (such that the program and erase couplings to each respective floating gate 14 are decoupled), and a source region formed below the common erase gate. In this cell, the source region may be formed before forming the word lines 20 and the coupling gate 22. During the source implant, the portions of each floating gate 14 that are not masked by resist are relatively unprotected, such that a portion of the source dopant may penetrate through each football oxide 16 and into each underlying floating gate 14, which may result in a dulling or blunting of the floating gate tips 15 located over the source region, as discussed above.